1. Field of Invention
This present invention is directed to phase and/or frequency locked loops, more particularly, to filterless digital phase and/or frequency lock loops.
2. Discussion of Related Art
As is well known in the electrical arts, a phase-locked loop (PLL) is a closed-loop feedback control system that generates and outputs a signal in relation to the frequency and phase of an input signal referred to in the art as a “reference” signal. Phase locked loops are widely used for synchronization and other purposes in a variety of applications. For examples, phase locked loops are used in communications for coherent carrier tracking, for bit or symbol synchronization, as master clock synthesizers for microprocessors, and in frequency synthesizers to generate new frequencies that are multiples of the reference signal frequency.
A phase-locked loop circuit responds to both the frequency and the phase of the input signals by automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference signal in both frequency and phase. Referring to FIG. 1, a block diagram shows one example of a conventional phase locked loop. The phase locked loop 100 includes a frequency synthesizer 102 that generates an output clock signal on line 104 from signal provided by a local oscillator 106, as known to those skilled in the art. The output clock signal is fed to a divide-by-N circuit 108, which produces a feedback signal having a frequency that is a multiple (1/N) of the frequency of the output clock signal. This feedback signal is fed to an error detector 110 which also receives a reference signal via line 112. The error detector 110 provides an error signal based on differences between the phase of the reference signal and the feedback signal. This error signal is filtered by a loop filter 114 (such as an FIR or IIR filter) and provided to the frequency synthesizer 102. Based on the error signal, the frequency synthesizer adjusts the phase and/or frequency of the output signal so as to maintain a lock with the reference signal.
The loop filter 114 is generally required to filter the error signal to stabilize the loop 100 and to reduce jitter in the output clock signal. In many instances, if the frequency synthesizer 102 were to adjust the output clock signal to compensate for the entire measured phase error during every cycle, a significant amount of jitter would be visible on the output clock signal. Therefore, the loop filter 114 is provided to reduce or eliminate components of the error signal in order to make the output clock corrections smaller, thereby reducing high frequency jitter on the output clock.